1. Field of the Invention
This invention relates to an error correction circuit and more particularly to an error correction circuit which is based on a neural network model.
2. Background of the Invention
A data processing system made of conventional logic circuits is getting bigger in size and more complex in its arrangement of components. As a result, increasing circuit complexity creates unexpected problems and rising manufacturing costs.
In addition, the need to improve accuracy and reliability of every block in the system or its respective subsystems, demands that techniques for providing error correction be included. However, systems based on simple logic circuits have performance limitations due to inherent property characteristics of logic gates.
To overcome such limitations of logic circuit technologies a system design based on the concept of a neural network model has been actively studied.
An error correcting system based on neural network principles is shown in FIG. 1. This system was presented in the IEEE first annual international conference on neural networks in June 1987, which has a reference number of IEEE catalog #87TH0191-7, by Yoshiyasu Takefuji, Paul Hollis, Yoon Pin Foo, and Yong B. Cho.
The error correcting system presented at the above conference uses the concept of neural network principles, based on the Hopfield model, and discloses a circuit which performs significantly faster than prior error correcting systems.
However, since the circuit by Yoshiyasu Takefuji et al. uses operational amplifiers as neurons and a passive resistor element network to form synapses, VLSI implementation is quite limited. The reason being that on a semiconductor integrated circuit, a resistor element network has high power consumption and thus hinders manufacturing of a high integration circuit design.
Furthermore, the above circuit is further inadequate since it requires additional interfacing circuitry added whenever a digital system based on NMOS and CMOS technologies is coupled thereto.